In semiconductor memory devices, data is read from or written to the memory using address signals and various other control signals. In random access memories (“RAMS”), an individual binary data state (e.g., a bit) is stored in a volatile memory cell, wherein a number of such cells are grouped together into arrays of columns and rows accessible in random fashion along bitlines and wordlines, respectively, wherein each cell is associated with a unique wordline and bitline pair. Address decoder control circuits identify one or more cells to be accessed in a particular memory operation for reading or writing, wherein the memory cells are typically accessed in groups of bytes or words (e.g., generally a multiple of 8 cells arranged along a common wordline). Thus, by specifying an address, a RAM is able to access a single byte or word in an array of many cells, so as to read or write data from or into that addressed memory cell group.
Two major classes of random access memories include “dynamic” (e.g., DRAMs) and “static” (e.g., SRAMs) devices. For a DRAM device, data is stored in a capacitor, where an access transistor gated by a wordline selectively couples the capacitor to a bit line. DRAMs are relatively simple, and typically occupy less data, because the charge stored in the cell capacitors tends to dissipate. Accordingly DRAMs need to be refreshed periodically in order to preserve the content of the memory. SRAM devices, on the other hand, do not need to be refreshed. SRAM cells typically include several transistors configured as a flip-flop having two stable states, representative of two binary data states. Since the SRAM cells include several transistors, however, SRAM cells occupy more area than do DRAM cells. However, SRAM cells operate relatively quickly and do not require refreshing and the associated logic circuitry for refresh operations.
A major disadvantage of SRAM and DRAM devices is volatility, wherein removing power from such devices causes the data stored therein to be lost. For instance, the charge stored in DRAM cell capacitors dissipates after power has been removed, and the voltage used to preserve the flip-flop data states in SRAM cells drops to zero, by which the flip-flop loses its data. Accordingly, SRAMs and DRAMs are commonly referred to as “volatile” memory devices. Non-volatile memories are available, such as Flash and EEPROM. However, these types of non-volatile memory have operational limitations on the number of write cycles. For instance, Flash memory devices generally have life spans from 100K to 10MEG write operations.
Recently, non-volatile ferroelectric RAM devices have been developed, which are commonly referred to as FERAMs or FRAMs. FERAM cells employ ferroelectric cell capacitors including a pair of capacitor plates with a ferroelectric material between them. Ferroelectric materials have two different stable polarization states that may be used to store binary information, where the ferroelectric behavior follows a hysteresis curve of polarization versus applied voltage. FERAMs are non-volatile memory devices, because the polarization state of a ferroelectric cell capacitor remains when power is removed from the device. Ferroelectric memories provide certain performance advantages over other forms of non-volatile data storage devices, such as Flash and EEPROM type memories. For example, ferroelectric memories offer short programming (e.g., write access) times and low power consumption. However, access times in SRAM and DRAM type memories are significantly shorter than in FERAM devices.
Hybrid memory devices have been developed, which include volatile and non-volatile portions. For example, memories have been constructed combining SRAM cells with ferroelectric devices, wherein the memory may be operated as an SRAM, with the capability to backup or save the volatile single SRAM data bit to a ferroelectric capacitor associated with the SRAM cell. The non-volatile data may thereafter be retrieved from the ferroelectric capacitor and transferred to the SRAM cell. In the interim, the SRAM cell may be operated as normal SRAM, even while non-volatile data resides in the ferroelectric capacitor. However, conventional hybrid memory devices store only a single non-volatile bit per cell. Thus, there is a need for improved hybrid memory devices and methods by which more than one non-volatile data state may be stored.